Field of Invention
This invention is related to an electrostatic discharge (ESD) protection circuitry. More particularly, the invention relates to an electrostatic discharge (ESD) protection circuitry that can be used in a radio frequency (RF) circuitry for electrostatic discharge protection.
Electrostatic discharge (ESD) is a transient process of high-energy transfer from integrated circuit (IC) outside to inside when the IC is floated. On-chip ESD protection circuits are constructed into the IC to withstand such destructive currents. The total discharge process takes about ˜1 μs for a human-body-model (HBM). In addition to HBM, there is also charged-device model (CDM) and machine model (MM). Several hundred volts are transferred during such ESD stresses. Voltage transition of this magnitude will make the gate oxide of input stage breakdown and render an IC mailfunction. As the thickness of gate oxide is scaled down constantly with advancements in sub-micrometer-fabrication processes, it is vital to improve the design of ESD protection circuits.
A traditional ESD protection design is a two-staged protection structure for digital IC, which is shown in FIG. 1. Between a primary stage 10 and a secondary stage 20 of an input ESD protection circuit, a resistor 15 is added to limit the ESD current flowing through a short-channel NMOS 25 in the secondary stage 20. The resistance value of the resistor 15 is dependent on the turn-on voltage of the ESD clamp device in the primary stage 10 and the current It2 (secondary breakdown current) of the short-channel NMOS 25 in the secondary stage 20. Such a two-staged ESD protection design can provide high ESD level protection for digital input pins. However, the large series resistance and the large junction capacitance in the ESD clamp devices will cause a long RC timing delay to the input signal. Therefore, this design is not suitable for analog pins, especially for radio frequency (RF) signal applications.
Due to the features of the high frequency applications, parasitic capacitance of the ESD protection device will degrade the power gain performance of RF circuits. In order to solve this problem, the prior art tried to minimize the area of the ESD protection device to reduce the parasitic capacitance of the ESD protection device. This solution, however, also degrades the ESD protection level, so it is necessary to minimize the effects of the parasitic capacitance of the ESD clamp devices for the RF circuits.
Some protection circuits have been proposed to achieve the above objectives, as follows.
Reversed-Biased Diodes with VDD-to-VSS Power-Rail Clamp Circuit
In order to reduce the loading capacitance to an input pin of RF circuits, diodes in the ESD protection circuits are designed with a small device dimension. With a small device dimension, the NDIO (PDIO) diode under the PS-mode (ND-mode) ESD stress (shown in FIG. 2) operates in the junction breakdown to discharge the ESD current. Typically, the diode under breakdown operation can only offer a low-level ESD protection. To avoid the small diodes from operating under breakdown condition during the PS-mode and ND-mode ESD stresses, and thus limit the ESD protection level of the entire circuit, a turn-on efficient ESD clamp circuit is inserted between the power rails to significantly increase the overall ESD protection level. The ESD circuit structure is shown in FIG. 3.
When the RF input pin is zapped with NS-mode (PD-mode) ESD stress, the NDIO (PDIO) diode operates under a forward-biased condition to discharge the ESD current. The diodes operating under the forward-biased condition can sustain a much higher ESD level than those operating under a reverse-biased breakdown condition. The RC-based ESD detection circuit 30 is used to trigger on the MNESD device, when the RF INPUT PAD 400 is zapped with the PS-mode or ND-mode ESD stress. The ESD current paths in this RF ESD protection design, under the PS-mode and ND-mode ESD stresses, are respectively illustrated by the dashed lines IESD in FIG. 4 and FIG. 5. Because the NDIO diode in the PS-mode ESD stress is not operating under the breakdown condition, the ESD current is bypassed through the forward-biased PDIO diode and the turned-on MNESD between the VDD/VSS power rails. Similarly, the ND-mode ESD current is discharged as the dashed line illustrates in FIG. 5 with the NDIO diode operating under a forward-biased condition and the turned-on MNESD between the VDD/VSS power rails. The MNESD is especially designed with a larger device dimension to sustain a high-level ESD. Although the large-dimension MNESD has a large junction capacitance, the capacitance does not contribute to the RF INPUT PAD 400. By using this ESD protection design, the RF INPUT pin can sustain much higher ESD levels under the four modes of ESD stresses, but only with small diodes connected to the RF INPUT PAD 400. This can reduce the loading capacitance generated from the ESD protection devices to the RF INPUT PAD 400.
Use of Inductor as an ESD Device
The Leuven University proposed a paper about LNA circuits with inductors and VDD-to-VSS dual stacked diodes to against the ESD discharge. The inductor is a metallic low-pass passive device and is suitable for ESD protection devices. However, since the inductor is connected from the input to the ground, it will cause DC leakage from the input to the ground directly. Therefore, it needs to be coupled with a capacitor, in series, to block the input PAD and the input gate.
Distributed ESD Protection Device for High-Speed Integrated Circuits
Shown in FIG. 6 and FIG. 8 are distributed ESD protection devices for high-speed integrated circuits, which are inventions by Stanford University. FIG. 6 shows a one-stage matching structure 45, and FIG. 8 shows a four-stage matching structure, including 45a, 45b, 45c and 45d. FIG. 7 shows a trace in Smith Chart of parasitic capacitance of the ESD within a one-stage distributed matching structure, and FIG. 9 shows the same capacitance in a four-stage distributed matching structure. In FIG. 7, the parasitic capacitance of ESD (CA+CB) traverses down its path following the circle in Smith Chart from the origin. A transmission line TL will bring the path to the x-axis of Smith Chart. In FIG. 9, the parasitic capacitance (C4A+C4B) traverses down its path following the circle in Smith Chart from the origin. The transmission line TL4 will bring the route to the x-axis of Smith Chart. The same concept can be applied to illustrate the other parasitic capacitance (C3A+C3B), (C2A+C2B), and (C1A+C1B). The transmission lines TL3, TL2, and TL1 will bring their routes to the x-axis of Smith Chart.(C1A+C1B)=(C2A+C2B)=(C3A+C3B)=(C4A+C4B)
A comparison of FIG. 7 and FIG. 9 shows that the more matching stages in the protective circuit, the closer the last position of the route is to the origin. The distance of the position to the origin is proportional to the signal power gain. Hence, having conditions with more stages matching leads to a better power gain. But it is hard to achieve uniform ESD current distribution amongst the numerous separated ESD sections during impulsive ESD events. The first ESD section, which is the closest to the input pad, will always receive the most bulk of the ESD current before the other sections are turned on to share the current. This causes damage to the first section and, ultimately, lowers the ESD protection threshold in the IC.